This invention relates generally to wafer defect detection systems and more particularly, it relates to an apparatus and method for introducing an on-wafer calibration structure on a semiconductor wafer to be inspected for use with a patterned wafer defect detection system so as to quickly and accurately calibrate the sensitivity of the detection system. Specifically, the present invention has particular application in patterned wafer defect detection systems or defect inspection tools which use image subtraction to detect defects on the surface of the semiconductor wafer.
As is generally known, the fabrication process of semiconductor integrated circuits involves a sequence of stages or steps which are used to convert a wafer of semiconductor material into a device(s) having a plurality of layers in which each layer has a particular pattern of circuit elements and interconnections. Since defects on the surface of a wafer layer that has been patterned will be detrimental to the quality of the manufactured semiconductor devices, semiconductor device manufacturers have utilized extensively defect detection systems for detecting defects on processed wafers of semiconductor material during each stage of the fabrication process. Thus, patterned defect inspections are regularly performed a number of times during the manufacturing process of a semiconductor device.
The defect detection systems or defect inspection tools are typically capable of being operated in two modes of operation so as to inspect the wafer for defects: (1) array mode and (2) random mode. In the array mode, a highly repetitive set of structures (such as those typically found in a RAM or memory device) are inspected by defining a cell comprising a subset of the repeating structure. This cell is compared to the cells on both the left and right sides of it and defects are detected as a difference between the subtraction of one cell from its neighboring cell. In the random mode, random structures (such as those found in a logic device) are inspected by defining an entire die or portion thereof) as a cell. This die is compared to the dice on both the left and right sides of it and defects are detected as a difference between the subtraction of one die from its neighboring die.
In order to accurately measure and detect the defects on the semiconductor wafer, the defect inspection tool must be accurately calibrated so as to prevent false detections. Therefore, once the cells are defined for the inspection, the sensitivity of the defect inspection tool must be adjusted or tuned in order to maximize the detection of the processing defects. Further, this adjustment must be performed repeatedly and individually on each defect inspection so as to optimize its sensitivity for detecting of the processing defects at each stage of the fabrication process at that point. Since the sensitivity of the defect inspection tool is a function of a number of factors, such as type of defects on the semiconductor wafer, number of patterned layers formed on the wafer, and so on, this complicates the calibration process for different wafers and for different types of wafer inspection tools.
The current procedure involves an iterative process of increasing the sensitivity of the defect inspection tool, scanning the wafer to detect for false defects, decreasing slightly the sensitivity, and scanning the wafer again to check that the false defects are no longer detected. As can be seen, this prior art technique is a very time-consuming operation during the different stages of the fabrication process and thus increases manufacturing costs.
The inventor is unaware of a calibration method which allows an operator or user of a defect inspection tool to know the smallest size defect that is detected by the defect inspection tool for each inspection in a semiconductor manufacturing process. Accordingly, it would be desirable to provide an on-wafer method and apparatus for calibrating the sensitivity of a patterned defect inspection tool during set-up so as to detect defects of known sizes. Further, it would be expedient that the on-wafer method and apparatus for calibrating the sensitivity of the patterned defect inspection tool allow direct comparison of different inspection tools at the various stages of the fabrication process. This is accomplished in the present invention by introducing a calibration structure having intentionally-introduced defects onto the wafer which is scanned during the defect inspection recipe setup or during each defect inspection.
Accordingly, it is a general object of the present invention to provide an apparatus and method for introducing an on-wafer calibration structure on a semiconductor wafer to be inspected which overcomes the disadvantages of the prior art calibration techniques.
It is an object of the present invention to provide an improved apparatus and method for introducing an on-wafer calibration structure on a semiconductor wafer to be inspected.
It is another object of the present invention to provide an apparatus and method for introducing an on-wafer calibration structure on a semiconductor wafer to be inspected for use with a wafer defect detection tool so as to quickly and accurately calibrate the sensitivity thereof.
It is still another object of the present invention to provide an apparatus and method for introducing an on-wafer calibration structure on a semiconductor wafer to be inspected which includes a plurality of intentionally-introduced defects each being of a progressively smaller size dimension.
In a preferred embodiment of the present invention, there is provided an on-wafer method for calibrating the sensitivity of a patterned wafer defect inspection tool during setup which is used to detect defects on the surface of a semiconductor wafer during the stages of a fabrication process. A semiconductor wafer which is to be inspected for defects is provided. A calibration structure is introduced which has known defects disposed on a selected area of the semiconductor wafer which is to be inspected for defects prior to the inspection. The semiconductor wafer with the calibration structure is loaded into the defect inspection tool.
The semiconductor wafer is aligned with respect to the defect inspection tool. Areas of the semiconductor wafer to be inspected are determined. The sensitivity of the defect inspection tool is adjusted to the desired scanning sensitivity setting. The sensitivity of the defect inspection tool is calibrated by scanning the semiconductor wafer with the calibration structure in order to determine the known defects which can be detected.